RX_FIFO_FULL_HLD_CTRL=Val_0x0, MASTER_MODE=Val_0x0, IC_10BITADDR_MASTER_RD_ONLY=Val_0x0, TX_EMPTY_CTRL=Val_0x0, IC_RESTART_EN=Val_0x0, STOP_DET_IF_MASTER_ACTIVE=Val_0x0, BUS_CLEAR_FEATURE_CTRL=Val_0x0, STOP_DET_IFADDRESSED=Val_0x0, IC_SLAVE_DISABLE=Val_0x0
Control Register
| MASTER_MODE | This bit controls whether the I2C master is enabled. NOTE: Software should ensure that if this bit is set to 1, bit IC_SLAVE_DISABLE should also be set to 1. 0 (Val_0x0): Master mode is disabled 1 (Val_0x1): Master mode is enabled |
| SPEED | These bits control at which speed the I2C operates; its setting is relevant only if the I2C operates in Master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for Slave mode also, as they are used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to 2. 1 (Val_0x1): Standard mode of operation 2 (Val_0x2): Fast or Fast Plus mode of operation |
| IC_10BITADDR_SLAVE | When acting as a slave, this bit controls whether the I2C responds to 7-bit or 10-bit addresses. 0x0: 7-bit addressing. The I2C ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the I2C_SAR register are compared. 0x1: 10-bit addressing. The I2C responds to only 10-bit addressing transfers that match the full 10 bits of the I2C_SAR register. 0x0: Slave 7-bit addressing 0x1: Slave 10-bit addressing |
| IC_10BITADDR_MASTER_RD_ONLY | The function of this bit is handled by I2C_TAR[IC_10BITADDR_MASTER] bit, and it is read only. 0 (Val_0x0): Master 7-bit addressing mode 1 (Val_0x1): Master 10-bit addressing mode |
| IC_RESTART_EN | Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions:
0 (Val_0x0): Master restart disabled 1 (Val_0x1): Master restart enabled |
| IC_SLAVE_DISABLE | This bit controls whether I2C has its slave disabled. If this bit is set, the Slave mode is disabled, and I2C functions only as a master; it does not perform any action that requires a slave. Software should ensure that if this bit is set to 0, then bit MASTER_MODE should also be set to 0. 0 (Val_0x0): Slave mode is enabled 1 (Val_0x1): Slave mode is disabled |
| STOP_DET_IFADDRESSED | In Slave mode: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address. 0 (Val_0x0): Issues the STOP_DET irrespective of whether it is addressed or not. 1 (Val_0x1): Issues the STOP_DET interrrupt only when it is addressed. |
| TX_EMPTY_CTRL | This bit controls the generation of the TX_EMPTY interrupt, as described in the I2C_RAW_INTR_STAT[TX_EMPTY]. 0 (Val_0x0): Default behaviour of TX_EMPTY interrupt 1 (Val_0x1): Controlled generation of TX_EMPTY interrupt |
| RX_FIFO_FULL_HLD_CTRL | This bit controls whether I2C should hold the bus when the Rx FIFO is physically full to its IC_COMP_PARAM_1[RX_BUFFER_DEPTH]. 0 (Val_0x0): Overflow when RX_FIFO is full 1 (Val_0x1): Hold bus when RX_FIFO is full |
| STOP_DET_IF_MASTER_ACTIVE | In Master mode: 0 (Val_0x0): Master issues the STOP_DET interrupt irrespective of whether master is active or not. 1 (Val_0x1): Master issues the STOP_DET interrupt only when master is active. |
| BUS_CLEAR_FEATURE_CTRL | In Master mode: In Slave mode this bit is not applicable. 0 (Val_0x0): Bus Clear Feature is disabled. 1 (Val_0x1): Bus Clear Feature is enabled. |